Performance Analysis of a Time-interleaved Sampling Architecture for a Software Defined Ultra Wideband Receiver

A Software Defined Radio for Ultra Wideband (UWB) communication systems places several stringent requirements on the Analog to Digital Converter (ADC). The ADC must have a sufficiently fast sampling frequency and SNR to accurately reconstruct the received UWB pulse. Such an ADC can be prohibitively expensive, as well as challenging to interface with a DSP or FPGA. An alternative approach is to sample the received signal with multiple slower ADCs operating on interleaved sampling clocks. Such a system operates as if it were a single ADC operating at a much higher sampling rate; however, gain, offset, and timing mismatches can significantly degrade the overall system performance. This paper presents simulation results for UWB pulses sampled using an 8-ADC Time Interleaved Sampling architecture running at an aggregate sampling rate of 8 GS/s. The results indicate that the performance of the system is primarily constrained by ADC gain and timing mismatches.